(1) Field of the Invention
This invention relates to checking systems, and particularly to an improved system for checking the reception and width of pulses used in synchronously timing the various subsystems in a data processor. These arrangements, usually known as "clock" systems, generally comprise a master or central pulse generator, which through the medium of various frequency dividing circuits, counters, and the like, generates a plurality of synchronizing signals which are supplied throughout the data processor to synchronize the operation of the various portions of the processor.
(2) Description of the Prior Art
There are numerous items of prior art relating to pulse checking circuitry for checking the sequence and duration of pulse trains, but none which specifically provide a pulse distribution system of the type herein disclosed, nor a pulse width arrival and checking system as also disclosed in the present application.